In general, vertical double diffused metal oxide semiconductor (DMOS) devices have a gate spaced from the active junction by a layer of gate oxide approximately 500-1000 angstroms thick. Because the gate is very close to the active junction and the channel, or drain, of the device, a relatively large capacitance, C.sub.GD, is formed between the gate and the drain of the device. This capacitance acts as a negative feedback path and limits the speed of switching of the device.
Further, in higher voltage vertical DMOS devices an epitaxial layer on the substrate in which the devices are formed is relatively lightly doped. This lightly doped region in the conductive path of the device increases the resistance of the device in the ON mode.